In word processors, personal computers, portable TVs, and the like, thin and light flat display devices are widely used. In particular, liquid crystal display devices are being actively developed because of the ease of reducing the thickness, weight, and power consumption thereof. Ones having high resolutions and large screen sizes have become available at relatively low prices.
Among liquid crystal display devices, active matrix liquid crystal display devices in which a thin film transistor (TFT) is placed as a switching element in the vicinity of each of the intersections between signal lines and scan lines are considered to become mainstream in the future because of their excellent color appearance and weak afterglow.
In a liquid crystal display device using amorphous silicon TFTs, tape carrier packages (TCPs) are used which are constructed by mounting signal line drive ICs and scan line drive ICs on flexible wiring boards. By electrically connecting these TCPs to external connection terminals of an array substrate, the signal line drive ICs and the scan line drive ICs are electrically connected to pixel electrodes on the array substrate, and pixel transistors are driven.
In this liquid crystal display device using amorphous silicon TFTs, a large number of interconnections are necessary for supplying picture signals from the TCPs to signal lines on an array substrate. Accordingly, in the case where the definition of pixels is improved, it is difficult to ensure a sufficient pitch between the interconnections. In this connection, for example, a technology described in Japanese Unexamined Patent Publication No. 2001-109435 has been known. In this technology, a signal line drive circuit is constructed using a switch circuit formed on an array substrate and signal line drive ICs mounted on TCPs. Each interconnection extended from the signal line drive ICs is connected to two adjacent signal lines one after another within one horizontal scan period using a pair of switches in the switch circuit, thus supplying the two signal lines with picture signals by time division.
In the above-described switch circuit, both of the source electrodes of a pair of switches are connected to a common interconnection extended from a signal line drive IC, the drain electrodes thereof are respectively connected to adjacent different signal lines, and the gate electrodes thereof are respectively connected to different switch control signal lines. Further, a signal line connected to the interconnection is switched according to switch control signals supplied to the gate electrodes.
The gate electrodes of the switches and the switch control signal lines are connected by electrode patterns. The electrode patterns are laid out in accordance with the positions of contact holes connected to the switch control signal lines. Accordingly, when attention is focused on a pair of switches, the left and right switches have different lengths from the switch control signal lines to the respective gate electrodes, and a difference occurs in the areas of the electrode patterns. Thus, the parasitic capacitances become unequal. Consequently, there is a difference between the times required to charge adjacent pixels with data signals. In some cases, display unevenness is caused.
Further, in the above-described layout, electrode patterns having different lengths are alternately arranged in a continuous manner. Accordingly, differences in length are difficult to find, and there is the problem that pattern abnormalities are difficult to find by visual inspection.
Furthermore, in the case where the connections between the electrode patterns and the switch control signal lines are changed, not only a contact hole formation layer but also the electrode patterns need to be changed. Along with this, a plurality of masks needs to be changed. Accordingly, there is the problem that a design change is expensive and that it is difficult to flexibly cope with a change to other drive system having a different connection form.